1. Field of the Invention
The invention relates to semiconductor test systems and methods, and more particularly, to semiconductor test systems and methods with improved maintenance properties and throughput.
2. Related Art
Various semiconductor testing technologies have been developed in order to improve the throughput of a test of semiconductor devices. Semiconductor test systems have been developed using test beds on which multiple devices can be connected and tested in parallel. The devices under test (DUTs) are provided with test pads at which a signal may be output, or from which a signal level may be input. The systems may execute test plans that program the signals to be applied to the devices and the signals that are to be read from the devices.
In an example of a semiconductor parametric test system that has been developed for use in process management of yield and transistors' electrical properties in the manufacture of integrated circuits, a test environment is included for improving software productivity. The test environment uses a tabular-form test plan, and program code provided as functions written in a general-purpose programming language or the like. The system executes test plans that are prepared by users and provided to the system in a table. The test plans are executed row-by-row where each row defines a function to be performed and information used by the function. The functions and information used by the functions are indicated as entries in the row according to the columns that define the function and associated information.
The semiconductor parametric test system enables the testing of devices in groups. A test element group (TEG) is defined as the measurement object of the test plan. Devices that belong to the TEG are setup for testing in a test environment that provides access to the test pads on the devices. The test determiners how the test pads are to be connected to a source measurement unit (“SMU”), which is controlled under program control by a processor. The connection from the test pad to the SMU is typically made by probing the device using a wafer prober. Each SMU is a measuring instrument capable of voltage application and current measurement, or of current output and voltage measurement. SMUs may be programmed to function by limiting current during voltage application as well as of limiting voltage during current output.
An example of a test plan based on the test environment of the semiconductor parametric test system that enables testing of devices in groups is illustrated in FIG. 6. The test plan shown in FIG. 6 is an example test plan for testing a TEG 820 depicted as the measurement object in the measurement block diagram in FIG. 7.
Referring to FIG. 7, the TEG 820 includes a first pad 804, a second pad 806, a third pad 808, and a fourth pad 810. The TEG 820 also includes a transistor TR4 802, which is an FET having a gate terminal ‘g’ connected to the first pad 804 on the TEG 820. The first pad 804 is connected to an SMU2 812, which has a port labeled ‘G.’ The transistor TR4 802 has a drain terminal ‘d’ connected to the second pad 806 on the TEG 820. The second pad 806 is connected to an SMU1 814, which has a port labeled ‘D.’ The transistor TR4 802 has a source terminal ‘s’ connected to the third pad 808 on the TEG 820. The third pad 808 is connected to an SMU3 816, which has a port labeled ‘S.’ The transistor TR4 802 has a substrate (bulk) terminal ‘sub’ connected to the fourth pad 810 on the TEG 820. The fourth pad 810 is connected to an SMU4 818, which has a port labeled ‘Sub.’ The respective physical connections from the SMUs 812-818 to the pads 804-810 are established by probing with the use of a wafer prober or the like.
The semiconductor parametric test system performs tests according to test plans prepared by users. The test plans have columns defining parameters and functions to be performed in a step of the test plan. For example, a column is included for identifying a module name for a grouping of circuits or devices that have pads to be probed together in one touchdown. Another column defines a function or measurement function to be executed during a particular step in the test plan. The row determines the step in the test plan, and the measurement function entry in the measurement function column identifies the particular program unit or units that are called for execution. The measurement functions are typically provided in a function library that is part of the software operating on the system. The measurement functions are typically written in a compiled programming language, such as the ‘c’ programming language. An example of how the rows and columns in a test plan table are used to execute the test plan is described with reference to FIG. 6.
Referring to FIG. 6, a test plan input window 600 has a test plan input area 614, where each row includes one measurement function, and the input and output parameter settings to be used with the function. The test plan 600 of FIG. 6 is configured as a program in the form of a table that executes an aggregation of one or more rows as steps in the program. The first column of the test plan 600 in FIG. 6 is indicated as being a ‘#’ column. The ‘#’ column allows a user to “comment out” a row by entering an “#” in the ‘#’ column for the selected row. When an ‘#’ is entered in the ‘#’ column, that row is not executed. The second and third columns, collectively indicated by 602, are used for symbol information used to identify location information of a measurement object on a semiconductor wafer. In the example illustrated in FIG. 6, a module name “Module B” is an entry used to identify the TEG 820 of FIG. 7. The example illustrated in FIG. 6 has the module name “Module A,” which refers to another TEG (not shown) as an entry in the second column, which is a module name column at 602. The test plan table 600 also has a device name “TR4,” which refers to the transistor TR4 802, entered in the device name column under the module name, “Module B,” of the TEG 820 of FIG. 7. Device names “TR1”, “TR2”, and “TR3” are entered in the device name column under the module name, “Module A.”
The test plan may include other columns, such as columns for providing input and output parameters, which are provided as arguments for function calls that invoke the measurement function identified in the measurement function column. Examples of the type of information that may be provided as input or output parameters include: values of electrical settings such as voltage or current, values of settings with terminal connection information, and pointers or memory storage indicators for storing data generated as output by the measurement function. The electrical settings provide the voltage and current values to be applied to the test pads in functional terms. For example, if the device tested is a transistor, the electrical settings would state values for the gate and the drain or source. The terminal information that may be provided as input parameters defines pads to be used for connections having a specific function. For example, a pad may be connected to the gate of a transistor being tested, or to the drain or source of the transistor.
The test plan 600 in FIG. 6 illustrates how measurement functions and their arguments are specified. The name of a measurement function or function may be entered in the “function” column 604. The measurement function entered in column 604 identifies a function for measuring a desired parameter of a measurement object that is specified in the column 602. In this example, function name ‘IOFF’ at 610 is entered in the measurement function column as a measurement function name. The function IOFF is, as described later with reference to FIG. 8, a measurement function for measuring a current that flows into a drain terminal of an FET device when specified voltages are applied to a gate terminal and a drain terminal of the FET device, and 0 (zero) V. is applied to a source terminal and a substrate terminal of the FET device. According to the measurement function entered in the measurement function column of this test plan, one FET identified in the device name column 602 of the test plan connected to a terminal specified in the pad number column in 606 of the test plan is measured by calling the measurement function ‘IOFF’ once.
The fifth, sixth, and seventh columns, which are collectively indicated by reference number 606 in FIG. 6 are used to specify input and output parameters for each measurement function specified in the measurement function column 604. The specified input and output parameters are arguments of the measurement function and the data specified in the arguments is used in function calls of the measurement function. In the example depicted in FIG. 6, the fifth column is an input column used for entering a list of values of mainly electrical settings information, such as voltage and current that does not include terminal connection information. The sixth column is a pad number column used for entering a list of values of settings information about terminal connection of a measurement object. The seventh column is an output column used for entering the label of a memory area for storing output data.
FIG. 6 illustrates examples of values for entry in the input column, pad number column and output column at 612. Values entered in the input column are to be passed to the measurement function ‘IOFF’ as a part of the input information on the measurement of TR4 that does not include terminal connection. The values entered in the input column include values for Vd (value of a voltage applied to the drain), Vg (value of a voltage applied to the gate), and a compliance value (limited current value). Values entered in the pad number column are values that define pad terminals of device TR4 that are to be connected to the gate connection terminal G, the drain connection terminal D, the source connection terminal S, and the substrate connection terminal Sub. In the output column, “Id4” is entered as the name of a memory area for storing an output of the measurement function ‘IOFF’ in association with an output parameter for the measurement function ‘IOFF.’ FIG. 8 is an example of the function ‘IOFF’ written in the ‘c’ programming language. The ‘IOFF’ function call definition includes a list of arguments 702 that are passed to the IOFF function when called. The arguments listed the list of arguments 702 correspond to the input parameters specified in the input column, the pad number column, and the output column at 612 in FIG. 6.
A tabular-form test plan of the type described above provides an environment that enables a user to program a test easily and intuitively. The user configures a test plan in a programming environment that consists of two layers in the form of a tabular-form test plan and a measurement function written in a general-purpose programming language. The test environment, which allows programming in a general-purpose programming language, also provides an environment compatible with any kind of programming. This type of test environment uses simple functions, but is limited in the tests that can be performed. This test environment is also not suitable for intricate and sophisticated program flow control that relies heavily on the use of conditional branching and repetition, nor for the programming of a function for a test that is more sophisticated than one prepared as a standard specification, or the like.
Another example of a semiconductor test system partially parallelizes a semiconductor parametric test. A test plan with parallel test attributes would include a parallel test attribute column in which labels are provided for specifying the start and end of parallelization. With the range of parallelization specified, a tester interprets the specified range, and generates threads so that tests are executed in a plurality of specified ranges in parallel to one another. The threads are each a series of steps in the test plan within the specified parallelization range performed for indicated devices in the TEG. An example of a test plan that performs parallelization is shown in FIG. 9. The test plan in FIG. 9 includes a parallel test attribute column 902 for entering labels, such as PT_SCHED_BEGIN and PT_SCHED_END, that define the start and end of parallelization. Two ranges of parallelization are shown in FIG. 9. The first range of parallelization 904 identifies a range of test steps for testing devices TR1 and TR2. A second range of parallelization 906 identifies a second range of test steps for testing devices TR2 and TR4.
However, this method, too, requires advanced knowledge and programming skill for semiconductor testing and test programs. This method also requires knowledge and performance of debugging.
Another example of a testing environment that uses a tabular-form test plan includes conditional branching processing using an IF statement, and repetition processing using a REPEAT statement. A LET statement may be included to assign a value to a parameter. Statements for invoking conditional processing may be added, for example, in the measurement function column described above.
An example of a test plan 2600 that uses conditional processing statements is illustrated in FIG. 10. The test plan 2600 follows a format similar to the test plan data entry area 2614 illustrated in FIG. 9. The conditional processing statements are entered in the measurement function column. FIG. 10 shows a REPEAT statement at 2610 to indicate that the rows that follow up until an UNTIL statement at 2616 are to be repeated until the condition for terminating the repetition specified in the input column for the UNTIL statement at 2618 is met. One of the statements in the range between REPEAT at 2610 and UNTIL at 2618 is the ‘IOFF’ function at 2612. The argument data at 2613 specified in the input column, pad number column, and the output column is provided in the repetition. The use of an IF statement at 2620 is provided in rows following the UNTIL statement at 2616. The condition for processing the rows that follow the IF statement at 2620 is indicated in the input column at 2622. The processing to be performed when the IF condition is met is provided in the next row at 2624, with corresponding arguments at 2626. An ELSEIF statement at 2628 is in the following row with data defining the ELSEIF condition at 2630. An ELSE statement at 2632 is shown around statements that set flags. An ENDIFF statement at 2634 defines the end of the IF-ELSEIF-ELSE blocks.
Test plans that include conditional processing statements have the effect of lengthening the test plan by the addition of rows that have a conditional processing statement in the measurement function column. The lengthening of the test plan and the addition of more rows makes a test plan less readable and more difficult to understand. In some test plans, numerous measurements are often repeated for statistical processing of measured values at different measurement conditions. Numerous measurements also make test plans more difficult to read or understand. Some test plans for certain types of TEGs also require steps for pre-processing and post-processing for a given measurement function. For example, a test plan may perform a measurement function for measuring the current output at a drain terminal of an FET device when specified voltages are applied to a gate terminal and a drain terminal of the FET device, while 0 (zero) V. is applied to a source terminal and a substrate terminal of the FET device. Before the measurement function is called, a function that sets the address of a desired TEG may be executed as pre-processing for a hundred TEGs. A function for resetting the voltage Vdd at the drain terminal may also be called after the measurement function as post-processing. Such pre- and post-processing steps further lengthen and complicate the display of test plans making them more difficult to read and understand. Test plans that are difficult to read or understand have the effect of complicating the tasks of debugging and correcting the test plan.
Test plans of the type described above also execute using an interpreter to call a measurement function in the measurement function column and to execute a command. Interpreted programs tend to execute slower in speed than compiled programs. The slower speed compared to the execution of a compiled program is particularly noticeable when repetition and conditional branching are repeated.
The execution speed could be improved by including branching, repetition, and other similar functions in a compiled measurement function. However, this would make such test plans inflexible since changes cannot be made after the program is completed. Another problem is that the maintenance of such test plans would have to be performed by a semiconductor engineer with a certain degree of advanced programming skill capable of comprehending the details of a measurement function. This requirement adds to the burden of test plan maintenance.
As has been described, the miniaturization and high degree of integration achieved in the semiconductor manufacturing process in recent years has resulted in the need to test an ever-increasing number of devices, the need for improvement in the throughput of the testing, and the need for an accompanying improvement in the maintenance properties of the test.